1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device and method thereof, and more particularly to a semiconductor memory device and method of performing a memory operation.
2. Description of the Related Art
A conventional semiconductor memory device may include memory cell arrays having a row and column array structure. Data may be read from or written to a given memory cell among the memory cell array in response to a read or write command if a row address and a column address designating the given memory cell are received.
Dynamic random access memory (DRAM) devices may be semiconductor memory devices which operate at higher operating speeds. Examples of DRAM devices may include synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, fast cycle RAM (FCRAM), etc.
In the SDRAM, an input/output of data may be valid only at a rising edge or falling edge of clock. Meanwhile, in the DDR SDRAM the input/output of date may be valid both at a rising edge and a falling edge of clock, thus the DDR SDRAM may have faster data transmission speeds as compared with SDRAM.
DDR DRAM may employ a DQ mask function, wherein DQ may indicate an input/output channel of data, and mask herein may mean to “cover” or protect data. A data masking signal DQM or DM signal may protect a given data portion such that the protected data portion may not be over-written during a write operation. In other words, an input/output for a portion of data may be disabled if the data masking signal corresponding to that data portion is activated.
In a conventional semiconductor memory device, an input/output of data may generally be controlled at a chipset level. During a data read command, data may be transferred from a memory cell to a central processing unit (CPU), and masking may be performed at the chipset itself such that data need not be actively masked. During a data write command, however, data may be transferred from a CPU to a memory cell, and the data portion to be protected may be masked so as not to be overwritten. Thus, data masking may typically be used only for write commands, and not read commands.
In conventional data masking processes masking data, an input/output driver may be controlled so as to load data on an input/output line, and a column selection line CSL may be controlled based on masking information, as will now be described in greater detail.
First, in the process of controlling an input/output driver, masking may be performed by turning off the input/output driver during a “normal” write operation which selects only one column selection line. Likewise, during a read operation, the input/output driver may be maintained in an off state such that the input/output line may be used for a read operation. However, the input/output driver may also be turned off when performing masking in a write operation by a unit of blocks to select a plurality of column selection lines, and the plurality of column selection lines may thereby be selected. Thus, cell data for the selected column selection lines may not be consistent, such that a memory failure may occur. Subsequently, in the process of controlling the column selection line CSL, if a data masking signal is input, a corresponding column selection line may be disabled, thus preventing data from being written to a particular memory cell.
FIG. 1 illustrates timings for a data masking operation in a conventional semiconductor memory device.
As shown in FIG. 1, if a write command signal W is applied, data D0,D1,D2,D3 and a data masking signal DM2 may be input after a given latency (e.g., 2 clock cycles). The data D0,D1,D2,D3 may be input sequentially, and if masking data in the data D0,D1,D2,D3 is a third data D2, data masking signal DM2 may be input concurrently with the third data D2. Likewise, if the second data D1 is to be masked, a second data masking signal DM1 may be input concurrently with the second data D1, and so on. That is, in the conventional semiconductor memory device, a write latency of the data D0,D1,D2,D3 and the data masking signal DM may be the same.
Referring to FIG. 1, the data D0,D1,D2,D3 may be processed in parallel by an internal write clock signal, and may be aligned as each internal data PDQ. While FIG. 1 illustrates data aligned by an external clock signal CLK instead of an internal clock signal, to the conventional semiconductor memory device may alternatively be configured to operate in response to an internal write clock signal which is synchronous to the external clock signal CLK. The internal write clock signal may be based on the external clock signal CLK, and in such situations the internal write clock signal may be alternatively represented by the external clock signal CLK. The data masking signal DM2 may also be aligned as an internal data masking signal PDM similar to that of the data D0,D1,D2,D3.
Referring to FIG. 1, the internal data D0,D1,D2,D3 may be aligned in parallel for a normal write operation if a column selection line corresponding to the data D0,D1,D2,D3 is enabled and the data D0,D1,D2,D3 may be transmitted to a memory cell through the column selection line CSL. However, if the internal data masking signal PDM to mask a write of third data D2 is provided, the column selection signal CSL_Q2 corresponding to the internal data masking signal PDM may not be enabled, even though the column selection lines CSL_Q0, CSL_Q1 and CSL_Q3 corresponding to the data D0, D1 and D3 may be normally enabled. In other words, a write operation may be designated only for the data D0, D1 and D3, while a write operation may also be performed for the third data D2 if the column selection line for the masking signal is not enabled.
Accordingly, a column selection line enable signal generator may be provided to enable or disable the column selection lines CSL in response to the data masking signal DM. An enable control of the column selection lines CSL_Q0, CSL_Q1, CSL_Q2 and CSL_Q3 may be performed by a column selection line enable signal generator 10 as shown in FIG. 2 (described below). The enable control of the column selection lines CSL_Q0, CSL_Q1, CSL_Q2 and CSL_Q3 may be performed in response to the clock signal CLK.
FIG. 2 illustrates a column selection line enable signal generator 10 in a conventional semiconductor memory device.
Referring to FIG. 2, the column selection line enable signal generator 10 may be provided at each column selection line within the conventional semiconductor memory device. The conventional column selection line enable signal generator 10 may include first and second inverters 112 and 114 and a NAND circuit NA10. The first inverter 112 may invert an inputted column selection line enable master signal PCSLMB. For example, if the first inverter 112 is enabled, the column selection line enable master signal PCSLMB may be output at a first logic level (e.g., a higher logic level or logic “1”) if the column selection line enable master signal PCSLMB is received at a second logic level (e.g., a lower logic level or logic “0”).
Referring to FIG. 2, the second inverter 114 may invert the internal data masking signal PDM. For example, if the second inverter 114 is enabled, the internal data masking signal PDM input at the second logic level (e.g., a lower logic level or logic “0”) may be inverted to the first logic level (e.g., a higher logic level or logic “1”).
Referring to FIG. 2, the NAND circuit NA10 may generate a column selection line enable signal PCSL_SELB as an output signal obtained by performing a logic operation (e.g., a Boolean logic operation such as a NAND operation) on an inverted signal of the column selection line enable master signal PCSLMB, an inverted signal of the internal data masking signal PDM and a column address signal CAij.
Referring to FIG. 2, the column selection line enable signal generator 10 may enable the column selection line enable signal PCSL_SELB if the column selection line enable master signal PCSLMB is set to the second logic level (e.g., before the inversion), the internal data masking signal PDM is set to the second logic level (e.g., before the inversion) and the column address signal CAij is set to the first logic level. If the column selection line enable signal PCSL_SELB is set to the second logic level (e.g., a lower logic level or logic “0”), the column selection line CSL may be enabled (e.g., set to the first logic level, such as a higher logic level or logic “1”).
Referring to FIG. 2, if data DQ is input and data masking signal DM is not input (or disabled), each column selection line CSL corresponding to the data may be enabled, and a write operation for the data may be performed. However, if the data masking signal DM is input (or enabled), a column selection line corresponding to the data may not be enabled and the data write operation may not be performed.
FIG. 3 illustrates timings for the data masking operation of FIG. 2.
Referring to FIG. 3, the column selection line enable master signal PCSLMB and the data masking signal PDM may be enabled in response to a clock signal CLK. Thus, if data is input, the column selection line enable master signal PCSLMB may be input to the column selection line enable signal generator 10 at the second logic level (e.g., a lower logic level or logic “0”). Further, the internal data masking signal PDM corresponding to the data may be enabled and input at the first logic level (e.g., a higher logic level or logic “1”). Accordingly, the column selection line enable signal PCSL_SELB may not be enabled and a column selection line CSL may not be enabled. If the internal data masking signal PDM is not enabled (e.g., maintained at the second logic level), and if the column selection line enable master signal PCSLMB is input at the second logic level, the column selection line enable signal PCSL_SELB may be enabled (e.g., set to the first logic level).
Referring to FIG. 3, the internal data masking signal PDM may be enabled (e.g., set to the first logic level) in order to mask data. In an example, the internal data masking signal PDM may be enabled to the first logic level in advance, before the column selection line enable master signal PCSLMB is enabled, so as to prevent a masking column selection line from being enabled. If an enabling of the internal data masking signal PDM is slower or delayed more than that of the column selection line enable master signal PCSLMB, a column selection line may not be masked, which may cause a “glitch” for a given period of time wherein external data may be inadvertently written into a memory cell (e.g., instead of being masked or prevented from writing).
Furthermore, if the internal data masking signal PDM is enabled and then disabled, the internal data masking signal PDM may be disabled before the column selection line enable master signal PCSLMB is enabled. Thus, if the internal data masking signal PDM is disabled for too long of a time period, the mask operation may prevent the execution of a “normal” (e.g., non-masked) write operation.
As shown in FIG. 3, the above-described masking defects which may cause write operation errors (e.g., not writing data during an approved write operation, writing data during a masked operation, etc.) may be reduced if first and second masking margins M1 and M2 are maintained at sufficient levels. However, it may be difficult to maintain the first and second masking margins M1 and M2 at such idealized levels, for example, due to factors in a physical layout structure of chips, environmental factors, etc.
For example, in a semiconductor memory device having a physical wiring layout structure in which a transmission time of the column selection line enable master signal PCSLMB is shorter than that of the internal data masking signal PDM, it may be difficult to ensure the lengths of the first and second masking margins M1 and M2 precisely. Furthermore, the first and second masking margins M1 and M2 may become inverted (e.g., negative) if the data DQ and data masking signal DM are set up by a clock signal at the same time, and an inverse-margin may occur by a difference of transmission time reaching to the column selection line enable signal generator 10.